Virtual N2-Class PDK

PDK tier: virtual_predictive — portability-focused, non-signoff virtual PDK.

This repository is a portability-focused, non-signoff virtual PDK for a hypothetical N2-class stacked nanosheet CMOS process.

It is intended for:

• architecture and RTL exploration
• early mixed-signal planning
• library and flow bring-up
• portability work before access to a real foundry kit

It is not intended for:

• manufacturing signoff
• foundry-faithful DRC, LVS, or extraction
• product EM, IR, ESD, aging, or yield closure

Evidence

The PDK's built-and-tested gates are committed artifacts, not prose:

• out/release_quality.json — release-assurance checks over the shipped benchmark metrics and scorecard axes (run_release_quality.sh).
• out/local_regression.json — the local regression gate set.
• pdk.lock.json — frozen real-PDK revisions and virtual-package provenance (pdkrs pdk-lock / pdkrs pdk-canary).
• Real-PDK verticals: out/sky130_vertical/summary.json (KLayout DRC + netgen LVS) and out/sky130_openroad/summary.json (Yosys → OpenROAD place + global route).
• The workspace evidence index: ../docs/EVIDENCE.md.

Technology stance

• logic-centric stacked nanosheet gate-all-around CMOS
• VDD_CORE = 0.70 V nominal
• threshold options: LVT, SVT, HVT, LONG
• discrete device sizing through sheet count, finger count, and optional longer channel selection
• macro-based SRAM instead of custom bitcell authoring

Repository layout

• python/pdkpy/data/source/: package-owned shipped source collateral, including models/, libs/, tech/, verification/, examples/, integrations/, and manifests/
• python/pdkpy/data/runtime/: packaged runtime fixture/output baseline surface used by installed package routes
• python/pdkpy/: installed Python package surface
• python/pdkpy/app/: source-tree maintenance and repo workflow helpers
• docs/: user, release, and backlog documentation
• out/: generated local outputs, summaries, and validation artifacts

Supported Product Surface

The supported public product surface is pdkrs and pdkpy.

• pdkrs: installed command entry point for the Rust-backed product routes
• pdkpy: installed Python package and companion command entry point for orchestration and ecosystem integration
• python/pdkpy/app/: source-tree maintenance and repo workflow helpers, not the supported public API
• sitecustomize.py: checkout-local development bootstrap only, not part of the supported installed product surface

From an installed environment, the shortest product-surface smoke path is:

python -m pip install -e .
pdkpy surface --json
pdkrs validate bindings --json
pdkrs validate acceptance --json
pdkrs validate manifests --json
pdkrs readiness score --json

For a concise map of the repo, see docs/repository-organization.md. For a command matrix that groups canonical virtual-PDK flows, product subsystem flows, and manufacturable-target alignment checks, see docs/run-matrix.md.

For release-candidate checks and the source/generated artifact policy, see docs/release-checklist.md and python/pdkpy/app/flow/run_release_artifact_policy.sh. For the CI-ready release-quality contract, see docs/release-quality-ci.md, manifests/release_quality.json, and python/pdkpy/app/flow/run_release_quality.sh.

For custom simulator developers, see docs/custom-simulator-integration.md, manifests/custom_simulator_contract.json, and python/pdkpy/app/flow/run_custom_simulator_contract.sh.

For a compact simulator onboarding corpus, see docs/golden-simulation-corpus.md, manifests/golden_simulation_corpus.json, and python/pdkpy/app/flow/run_golden_simulation_corpus.sh.

For a documentation index, see docs/README.md. For a test-suite index, see tests/README.md.

For the shortest executable path through the repo, see docs/quickstart.md. For support levels and what the repo does or does not claim, see docs/validation-policy.md.

Quick start

From the repository root:

python -m pip install -e .
pdkpy surface --json
pdkrs readiness score --json

These installed commands exercise the supported product surface directly. The source-tree flow wrappers below remain useful for broader repo maintenance and unported workflow coverage.

From the repository root, for source-tree workflows:

source python/pdkpy/app/env/setup.sh
python/pdkpy/app/env/check_toolchain.sh --require-openroad
python/pdkpy/app/sim/run_ngspice_smoke.sh
python/pdkpy/app/flow/run_spec_validation.sh
python/pdkpy/app/flow/run_characterization_consistency.sh
python/pdkpy/app/flow/run_yosys_smoke.sh
python/pdkpy/app/flow/run_klayout_drc_smoke.sh
python/pdkpy/app/flow/run_netgen_lvs_smoke.sh
python/pdkpy/app/flow/run_pv_stack.sh
python/pdkpy/app/flow/run_openroad_smoke.sh
python/pdkpy/app/flow/run_openroad_parity.sh
python/pdkpy/app/flow/run_sram_macro_integration.sh
python/pdkpy/app/flow/run_interoperability_stack.sh
python/pdkpy/app/flow/run_provenance_stack.sh
python/pdkpy/app/flow/run_reproducibility_stack.sh
python/pdkpy/app/flow/run_behavioral_model_stack.sh
python/pdkpy/app/flow/run_rf_flow.sh
python/pdkpy/app/flow/run_mixed_signal_cosim.sh
python/pdkpy/app/flow/run_rc_stack.sh
python/pdkpy/app/flow/run_benchmarks.sh
python/pdkpy/app/regress/run_local_regression.sh

The flow scripts fail cleanly if the required tools are not installed. run_openroad_smoke.sh also supports a Docker fallback using openroad/orfs by default.

For a deeper walkthrough of the collateral, flow assumptions, and how to extend the kit, see docs/tutorial.md.

For a shorter navigation guide across scripts, manifests, examples, configs, and generated outputs, see docs/repository-organization.md.

For the most common test and tutorial commands grouped by purpose, see docs/run-matrix.md.

For audience-specific tutorial tracks, also see docs/tutorial-novice-circuits.md, docs/tutorial-proprietary-users.md, docs/tutorial-open-source-users.md, and docs/tutorial-expert-reference.md.

For Ubuntu installation, offline setup, and primers on each FOSS tool used here, see docs/tooling-setup.md.

For local verification and one-command airplane prep, see python/pdkpy/app/env/check_toolchain.sh and python/pdkpy/app/env/prepare_offline_session.sh.

For the prioritized roadmap and active execution backlog, see docs/unaddressed/notes/README.md and the numbered notes under docs/unaddressed/notes/.

For the initial machine-readable PDK contract, see docs/spec/open-pdk-spec.md, manifests/pdk.json, and python/pdkpy/app/flow/run_spec_validation.sh.

For benchmark definitions and golden expectations, see benchmarks/README.md and benchmarks/golden/smoke_benchmarks.json.

For the generated Liberty methodology, consistency gate, and consumed advanced-characterization analysis, see docs/characterization.md, docs/advanced-characterization-consumption.md, libs/liberty/characterization/, python/pdkpy/app/flow/run_characterization.sh, python/pdkpy/app/flow/run_characterization_consistency.sh, and python/pdkpy/app/flow/run_advanced_characterization_consumption.sh.

For deterministic statistical mismatch and RC-variation proxy evidence, see docs/statistical-variation.md and python/pdkpy/app/flow/run_statistical_variation.sh.

For the shipped resettable, scan-capable, clock-gating, and physical-support cell strategy, see docs/low-power-and-support-cells.md.

For executable scan-chain, boundary-scan-style replay, and ATPG-facing metadata, see docs/dft-scan-atpg.md and python/pdkpy/app/flow/run_dft_scan_demo.sh.

For executable MBIST-style memory test, single-address repair replay, and ECC/parity detection collateral, see docs/mbist-repair-ecc.md and python/pdkpy/app/flow/run_mbist_demo.sh.

For SRAM retention/redundancy/fuse modeling boundaries built on that MBIST evidence, see docs/sram-retention-redundancy.md and python/pdkpy/app/flow/run_sram_retention_redundancy.sh.

For bounded formal proof, equivalence, coverage, and runtime-parity evidence, see docs/formal-coverage-runtime-parity.md and python/pdkpy/app/flow/run_formal_coverage.sh.

For the executable switched-domain power-gating demo and the remaining UPF/signoff boundary, see docs/power-gating.md, docs/upf-low-power-intent.md, and python/pdkpy/app/flow/run_power_gating_demo.sh.

For richer multi-design OpenROAD implementation results, parity summaries, and current upstream gaps, see docs/openroad-parity.md and python/pdkpy/app/flow/run_openroad_parity.sh.

For the broader physical-verification stack across KLayout, Netgen, and Magic, see docs/pv-stack.md and python/pdkpy/app/flow/run_pv_stack.sh.

For RC-aware digital and analog comparison benches plus routed pre-route-versus-routed timing deltas, see docs/rc-stack.md, python/pdkpy/app/sim/run_rc_impact_benchmarks.sh, and python/pdkpy/app/flow/run_rc_stack.sh.

For the compiler-style SRAM request matrix, generated macro views, and richer integration cases, see docs/sram-compiler.md, docs/sram-macro-integration.md, crates/pdkrs-cli/src/compile_sram_metadata.rs (pdkrs compile-sram-metadata), and python/pdkpy/app/flow/run_sram_macro_integration.sh.

For executable memory-cell and periphery foundation collateral beneath the current SRAM macro story, see docs/memory-foundation.md, libs/sram/foundation/README.md, and python/pdkpy/app/flow/run_memory_foundation.sh.

For canonical snapshot export plus source/runtime interoperability checks, see docs/interoperability.md, baselines/canonical/README.md, and python/pdkpy/app/flow/run_interoperability_stack.sh.

For licensing, provenance, and signed-manifest support, see docs/provenance.md, baselines/provenance/README.md, and python/pdkpy/app/flow/run_provenance_stack.sh.

For pinned environment baselines, profile definitions, and live environment validation, see docs/reproducible-environments.md, environments/README.md, and python/pdkpy/app/flow/run_reproducibility_stack.sh.

For reference Verilog-A sources plus the primary OpenVAF -> OSDI -> ngspice path and the secondary ngspice fallback models, see docs/behavioral-models.md, models/behavioral/README.md, and python/pdkpy/app/flow/run_behavioral_model_stack.sh.

For broader simulator-runtime parity and the current Xyce discovery boundary, see docs/simulator-runtime-parity.md, manifests/simulator_runtime_parity.json, and python/pdkpy/app/flow/run_simulator_runtime_parity.sh.

For editable xschem sources that map back to the current OTA, RF passive, and SAR8 mixed-signal flow anchors, see docs/xschem-projects.md and python/pdkpy/app/flow/run_xschem_project_stack.sh.

For product-style analog block examples built on the compiled behavioral-model stack, see docs/analog-reference-designs.md and python/pdkpy/app/flow/run_analog_reference_designs.sh.

For the current RF and high-frequency flow, touchstone artifacts, lumped EM proxies, and transient-periodic/phase-noise proxy reporting, see docs/rf-flow.md, examples/rf/topmetal_passives/README.md, manifests/rf_flow.json, and python/pdkpy/app/flow/run_rf_flow.sh.

For the reusable SerDes/PHY methodology foundation that later PCIe, Ethernet, and USB-C work builds on, see docs/phy-serdes-foundation.md, manifests/phy_serdes.json, and python/pdkpy/app/flow/run_phy_serdes_demo.sh.

For the real open manufacturable PDK target matrix that future Tiny Tapeout and multi-PDK work must reference, see docs/manufacturable-pdk-targets.md, manifests/manufacturable_pdk_targets.json, and python/pdkpy/app/flow/run_manufacturable_pdk_targets.sh.

For the product-style digital subsystem contract tying SRAM, CDC, low-power, power-gating, DFT, MBIST, and future Tiny Tapeout candidacy together, see docs/product-digital-subsystems.md, manifests/product_digital_subsystems.json, and python/pdkpy/app/flow/run_product_digital_subsystems.sh.

For the local Tiny Tapeout-style wrapper around the compact telemetry subsystem candidate, see docs/tiny-tapeout-reference.md, manifests/tiny_tapeout.json, and python/pdkpy/app/flow/run_tiny_tapeout_demo.sh.

For the current SKY130 / Tiny Tapeout evidence level for that wrapper, see docs/sky130-tiny-tapeout-evidence.md, manifests/sky130_tiny_tapeout_evidence.json, and python/pdkpy/app/flow/run_sky130_tiny_tapeout_evidence.sh.

For real sky130A physical-verification verticals, see docs/sky130a-lvs-vertical.md (KLayout extraction + netgen positive/negative), docs/sky130a-pex-vertical.md (Magic extraction vs schematic parity), docs/sky130a-pv-vertical.md (combined DRC + LVS + PEX), and docs/sky130a-openroad-vertical.md (Yosys map to sky130 cells then OpenROAD place + TritonRoute detailed route, routed-estimate timing). For the std-cell simulation leg, docs/gate-level-sim.md runs the mapped netlist through iverilog and compares it against the RTL cycle for cycle, and docs/digital-verification.md adds independent-engine verification (iverilog RTL + iverilog gate + Verilator RTL must agree, plus a Yosys formal RTL-to-mapped equivalence proof) and is wired into the pdk-2nm graphd gate plan. docs/gds-export.md converts the routed DEF into an abstract-view GDS (routing + via geometry checked by the abstract DRC deck, cell pin/label geometry preserved on side datatypes) and closes the gds_count = 0 handoff gap. docs/rtl-to-gds-demo.md composes the whole staged virtual_n2 flow (synthesis, place/CTS/detailed route, routed-estimate timing and power, GDS export + abstract DRC, gate-level simulation) into a single handoff report with explicitly unclaimed signoff-PEX and LVS stages. docs/sky130a-handoff.md composes the real-PDK sky130A legs (standard-cell LVS + DRC + Magic PEX, design connectivity LVS of the routed DEF against the synthesis netlist, Yosys synthesis to sky130_fd_sc_hd, OpenROAD tap cells + minimal PDN + place + detailed route with routed-estimate timing, gate-level functional simulation, and a routed-GDS export merged with the foundry cell GDS plus a foundry DRC report) into one per-PDK handoff report with only the signoff-PEX stage unclaimed; docs/sky130a-design-lvs.md documents the design-level connectivity LVS, and docs/sky130a-gds-export.md documents that routed-DEF-to-merged-GDS export, and docs/sky130a-gate-level-sim.md runs the sky130-mapped counter through iverilog against the RTL using the shipped functional cell models (no SDF timing), and docs/cocotb-counter.md runs the same counter test from Python through cocotb/icarus against the RTL and the sky130 gate netlist (cocotb is declared in the dev dependency group and installed by uv sync). docs/eqy-counter.md runs the YosysHQ EQY formal-equivalence lane (self-hosted ISC source build, tag pinned to the local Yosys) proving the virtual_n2 counter RTL against the mapped netlist with a SAT partition proof. The gf180mcuD repeat of the DRC + LVS + PEX vertical is docs/gf180mcu-pv-vertical.md (KLayout 51-table flat-mode DRC positive/negative, Magic extraction + netgen positive/negative, and capacitance-backed Magic PEX parity against the PDK schematic on gf180mcu_fd_sc_mcu7t5v0__inv_1); the gf180mcuD digital slice is docs/gf180mcu-openroad-vertical.md (Yosys map to gf180mcu_fd_sc_mcu7t5v0, OpenROAD place + TritonRoute detailed route with routed-estimate timing), docs/gf180mcu-gds-export.md (routed DEF merged with the foundry cell GDS plus Metal1-Metal5 foundry DRC reported) and docs/gf180mcu-gate-level-sim.md (iverilog functional parity, no SDF), and docs/gf180mcu-handoff.md composes all of those legs into one per-PDK handoff report with only the signoff-PEX stage unclaimed; the IHP SG13G2 repeat is docs/ihp-sg13g2-pv-vertical.md (KLayout maximal-runset DRC positive/negative plus Magic extraction + netgen positive/negative, and capacitance-backed PEX parity against the PSP103 schematic on sg13g2_inv_1), and docs/ihp-sg13g2-hbt.md exercises the SiGe HBT (npn13G2 VBIC) Gummel slope against nf · VT · ln(10) plus beta and quasi-saturation plausibility. The SRAM macro vertical, docs/ihp-sg13g2-sram.md, runs KLayout 0.30 deep-mode LVS on RM_IHPSG13_1P_256x8_c3_bm_bist with a worked negative control and a documented CDLYX1 representation residual, validates the shipped three-corner Liberty views, cross-checks LEF/Liberty/Verilog views plus Yosys blackbox elaboration, and extracts bitcell RC with Magic. docs/ihp-sg13g2-handoff.md composes all of the IHP SG13G2 legs (standard-cell DRC/LVS/PEX, the HBT analog breadth, the SRAM macro four-leg evidence, and the digital slice) into one per-PDK handoff report with only the extracted-simulation and signoff-PEX stages unclaimed; the digital slice is docs/ihp-sg13g2-openroad-vertical.md (Yosys map to sg13g2_stdcell, OpenROAD place + TritonRoute detailed route with routed-estimate timing), docs/ihp-sg13g2-gds-export.md (routed DEF merged with the foundry cell GDS plus maximal-runset DRC reported) and docs/ihp-sg13g2-gate-level-sim.md (iverilog functional parity via a generated functional cell view, no SDF). For the EM-result-to-circuit handoff on the topmetal transformer (coupled-inductor RLCK converted to its exact T model, gas run-sparams vs the ngspice Touchstone plus an analytic passivity bound), see docs/rf-circuit-coupling.md and python/pdkpy/app/flow/run_rf_coupling_demo.sh. For PDK-aware EM stackups, docs/pdk-em-stackups.md derives one normalized layer table per shipped open PDK (sky130A/gf180mcuD from tech-LEF THICKNESS/RESISTANCE RPERSQ/DCCURRENTDENSITY, IHP SG13G2 from the KLayout cross-section process steps plus LVS RSH_RES_*) and documents that guard-ring and patterned-shield effects are not modeled. For the P4.6 thermal probe, docs/thermal-probe.md couples simulated die power and routed-DEF power density from the virtual_n2 digital flow to the proxy package/board/enclosure budget, recomputes the first-pass junction estimate, and checks the package theta_ja against a published still-air BGA band. For the P4.7 SI report, docs/si-report.md couples the interconnect RC lane to timing and states pre-layout vs routed global-route estimate vs extracted-RC lanes, with coupling caps present but crosstalk timing, signoff extraction and transmission-line reflection explicitly unclaimed. For the predictive LambdaPDK demo packages, docs/predictive-lambda-pdks.md packages asap7 (7nm-class FinFET) and freepdk45 (45nm-class planar) as authored public-reference estimates with view placeholders, honesty labels and a documented no-signoff boundary.

For full gf180mcuD counter connectivity LVS, see docs/gf180mcu-design-lvs.md (routed DEF vs mapped netlist with a positive match and negative control; cell-internal transistors and well ties are excluded).

For full IHP SG13G2 counter connectivity LVS, see docs/ihp-sg13g2-design-lvs.md (routed DEF vs mapped netlist with a positive match and negative control; cell-internal transistors and well ties are excluded).

For the current GF180MCU and IHP SG13G2 evidence levels, see docs/gf180-ihp-target-evidence.md, manifests/gf180_ihp_target_evidence.json, and python/pdkpy/app/flow/run_gf180_ihp_target_evidence.sh.

For target-aware translated flow metadata across SKY130, GF180MCU, and IHP SG13G2, see docs/manufacturable-flow-matrix.md, manifests/manufacturable_flow_matrix.json, and python/pdkpy/app/flow/run_manufacturable_flow_matrix.sh.

For the machine-readable modernization scorecard that summarizes shipped, proxy, metadata-only, and translated-config support levels, see docs/modernization-scorecard.md, manifests/modernization_scorecard.json, and python/pdkpy/app/flow/run_modernization_scorecard.sh.

For the list of synthetic/self-validating verification machinery that is kept but must not be cited as signoff evidence (DRC/LVS/PEX regression runner, self-validating scorecard path, synthetic CCS/LVF packs, protocol compliance proxies), see quarantine/README.md (P0.7a).

For the first PCIe-oriented link-training, L0/L1/recovery, and TLP replay proxy built on that PHY foundation, see docs/pcie-subsystem.md, manifests/pcie.json, and python/pdkpy/app/flow/run_pcie_subsystem_demo.sh.

For the first Ethernet MAC/PCS-oriented subsystem proxy built on that PHY foundation, see docs/ethernet-subsystem.md, manifests/ethernet.json, and python/pdkpy/app/flow/run_ethernet_subsystem_demo.sh.

For the first USB-C / USB3-oriented attach, orientation, SuperSpeed-link, and low-power proxy built on that PHY foundation, see docs/usb-c-usb3-subsystem.md, manifests/usb.json, and python/pdkpy/app/flow/run_usb_subsystem_demo.sh.

For the reusable mixed-signal bridge harness spanning SAR8 replay and a trimmed-reference monitor example, see docs/mixed-signal-cosim.md, python/pdkpy/app/mixed_signal/run_sar8_cosim.py, python/pdkpy/app/mixed_signal/run_refmon_trim_cosim.py, and python/pdkpy/app/flow/run_mixed_signal_cosim.sh.

For the local-first regression gate, see docs/local-regression.md, manifests/local_regression.json, and python/pdkpy/app/regress/run_local_regression.sh.

First concrete artifacts included here

The abstraction class and fidelity boundaries of everything below are stated in docs/abstraction-class.md (geometry, device models, and the layer-map subset).

• Openly authored Verilog-A/OSDI device models (OpenVAF-compiled) plus a translated ngspice-friendly planar BSIM4 (level=14) fallback envelope and passive models
• starter SPICE wrappers for n2n_* and n2p_* devices
• starter core-cell SPICE, Verilog, Liberty, and LEF collateral
• resettable and scan-capable sequential cells plus a starter integrated clock-gate
• executable DFT scan replay collateral with internal scan, boundary access, and ATPG-facing pattern metadata
• executable MBIST memory-test replay collateral with SRAM macro access, repair remap, and ECC/parity detection checks
• explicit SRAM retention/redundancy/fuse metadata with executable MBIST-backed repair replay and no foundry fuse-programming claim
• bounded formal/property proof, exhaustive equivalence miter, and coverage/runtime-parity rollup evidence
• tie, filler, decap, antenna, tap, and endcap support-cell abstracts
• executable power-gating demo collateral with a switched-domain model, isolation, retention observation, and always-on support behavior
• example inverter-chain and OTA smoke benches
• abstract KLayout DRC and Netgen LVS smoke harnesses
• broader positive/negative PV suites for KLayout DRC, abstract Netgen LVS, and Magic trust-boundary probing
• synthesis, OpenROAD smoke, and multi-design implementation parity scripts wired to the chosen naming scheme
• RC-aware digital and analog comparison benches plus a validated RC-stack summary tying LEF RC, OpenROAD parasitic estimates, and SPICE impact together
• metadata-driven SRAM macro views plus a placed-and-timed sram_wrap32 integration example
• executable memory-cell and periphery foundation collateral tying the SRAM macro story back to a 6T bitcell and key row/column support blocks
• a compiler-style SRAM macro matrix plus a dual-port packet-buffer integration example
• a canonical interoperability snapshot plus runtime invariants for counter, gated_accum8, and sram_wrap32
• a provenance and licensing stack with deterministic source-manifest export, SHA-256 sidecars, and optional GPG signing helpers
• a reproducibility stack with a pinned validated-host tool and image baseline plus live environment validation
• a behavioral-model layer with reference Verilog-A sources plus compiled OSDI delivery and regression-backed fallback parity checks
• product-style analog reference blocks for a low-voltage trimmed reference and comparator family with machine-readable targets
• checked-in xschem project anchors for the OTA, RF passive benches, and the SAR8 mixed-signal correspondence surface
• an RF passive flow that generates S1P/S2P artifacts and validates passive quality trends against the behavioral VCO baseline
• executable SerDes/PHY lane methodology collateral with training, CDR/equalization proxies, loopback, and compliance-boundary reporting
• executable PCIe-oriented subsystem collateral with LTSSM, DLLP credit, L0/L1/recovery, and TLP acceptance checks
• executable Ethernet-oriented subsystem collateral with PHY link bring-up, PCS block-lock, MAC frame/FCS checks, and low-power idle replay
• executable USB-C / USB3-oriented subsystem collateral with Type-C attach/orientation, PD-ready, SuperSpeed link, recovery, and U1 wake checks
• a checked manufacturable-PDK target matrix for SKY130, GF180MCU, and IHP SG13G2 so future Tiny Tapeout and multi-PDK flows have a real contract surface
• a product-style digital subsystem contract aggregating SRAM-backed, CDC, low-power, power-gating, DFT, and MBIST examples with an explicit Tiny Tapeout candidate boundary
• a local Tiny Tapeout-style telemetry wrapper with pin-map, SKY/IHP target-family metadata, and an explicit no-submission boundary
• a SKY130 / Tiny Tapeout evidence contract showing local generic synthesis evidence while explicitly preserving no-submission, no-physical-verification boundaries
• a GF180MCU / IHP SG13G2 evidence contract that keeps those targets at translated-config support until real local implementation artifacts exist
• a multi-PDK manufacturable flow matrix with translated configs for sky130A, gf180mcuD, and ihp-sg13g2 across the counter, Tiny Tapeout wrapper, and telemetry subsystem examples
• a modernization scorecard that ties shipped capabilities, proxy boundaries, Tiny Tapeout status, and multi-PDK support levels into one checked contract
• a reusable mixed-signal bridge harness that reproduces SAR settling/trim behavior plus trimmed-reference monitor recovery through real RTL execution

Naming conventions

• core cells: n2_core__*
• IO cells: n2_io__*
• SRAM macros: n2_sram__*
• NMOS devices: n2n_*
• PMOS devices: n2p_*

Release caveat

This state is releaseable as an exploratory virtual PDK baseline. It is not a tapeout kit.