Virtual N2-Class PDK

This repository is a portability-focused, non-signoff virtual PDK for a hypothetical N2-class stacked nanosheet CMOS process.

It is intended for:

• architecture and RTL exploration
• early mixed-signal planning
• library and flow bring-up
• portability work before access to a real foundry kit

It is not intended for:

• manufacturing signoff
• foundry-faithful DRC, LVS, or extraction
• product EM, IR, ESD, aging, or yield closure

Technology stance

• logic-centric stacked nanosheet gate-all-around CMOS
• VDD_CORE = 0.70 V nominal
• threshold options: LVT, SVT, HVT, LONG
• discrete device sizing through sheet count, finger count, and optional longer channel selection
• macro-based SRAM instead of custom bitcell authoring

Repository layout

• models/process/: surrogate process-corner compact models
• models/passives/: passive abstractions
• libs/spice/: SPICE primitives and starter cell views
• libs/verilog/: functional digital library views
• libs/liberty/: starter timing library for open synthesis
• libs/lef/: abstract digital implementation views
• tech/: KLayout and Magic technology-view collateral
• verification/: abstract physical-verification collateral
• scripts/: environment and smoke-test runners
• examples/: starter digital, analog, and mixed-signal blocks

Quick start

From the repository root:

source scripts/env/setup.sh
scripts/env/check_toolchain.sh --require-openroad
scripts/sim/run_ngspice_smoke.sh
scripts/flow/run_spec_validation.sh
scripts/flow/run_characterization_consistency.sh
scripts/flow/run_yosys_smoke.sh
scripts/flow/run_klayout_drc_smoke.sh
scripts/flow/run_netgen_lvs_smoke.sh
scripts/flow/run_pv_stack.sh
scripts/flow/run_openroad_smoke.sh
scripts/flow/run_openroad_parity.sh
scripts/flow/run_sram_macro_integration.sh
scripts/flow/run_interoperability_stack.sh
scripts/flow/run_provenance_stack.sh
scripts/flow/run_reproducibility_stack.sh
scripts/flow/run_behavioral_model_stack.sh
scripts/flow/run_rf_flow.sh
scripts/flow/run_mixed_signal_cosim.sh
scripts/flow/run_rc_stack.sh
scripts/flow/run_benchmarks.sh
scripts/regress/run_local_regression.sh

The flow scripts fail cleanly if the required tools are not installed. run_openroad_smoke.sh also supports a Docker fallback using openroad/orfs by default.

For a deeper walkthrough of the collateral, flow assumptions, and how to extend the kit, see docs/tutorial.md.

For Ubuntu installation, offline setup, and primers on each FOSS tool used here, see docs/tooling-setup.md.

For local verification and one-command airplane prep, see scripts/env/check_toolchain.sh and scripts/env/prepare_offline_session.sh.

For the prioritized roadmap and open issues backlog, see docs/unaddressed/todos/README.md and the numbered items under docs/unaddressed/todos/.

For the initial machine-readable PDK contract, see docs/spec/open-pdk-spec.md, manifests/pdk.json, and scripts/flow/run_spec_validation.sh.

For benchmark definitions and golden expectations, see benchmarks/README.md and benchmarks/golden/smoke_benchmarks.json.

For the generated Liberty methodology and consistency gate, see docs/characterization.md, libs/liberty/characterization/, scripts/flow/run_characterization.sh, and scripts/flow/run_characterization_consistency.sh.

For the shipped resettable, scan-capable, clock-gating, and physical-support cell strategy, see docs/low-power-and-support-cells.md.

For richer multi-design OpenROAD implementation results, parity summaries, and current upstream gaps, see docs/openroad-parity.md and scripts/flow/run_openroad_parity.sh.

For the broader physical-verification stack across KLayout, Netgen, and Magic, see docs/pv-stack.md and scripts/flow/run_pv_stack.sh.

For RC-aware digital and analog comparison benches plus routed pre-route-versus-routed timing deltas, see docs/rc-stack.md, scripts/sim/run_rc_impact_benchmarks.sh, and scripts/flow/run_rc_stack.sh.

For metadata-driven SRAM macro generation plus a real integration case, see docs/sram-macro-integration.md, scripts/sram/generate_sram_views.py, and scripts/flow/run_sram_macro_integration.sh.

For canonical snapshot export plus source/runtime interoperability checks, see docs/interoperability.md, canonical/README.md, and scripts/flow/run_interoperability_stack.sh.

For licensing, provenance, and signed-manifest support, see docs/provenance.md, provenance/README.md, and scripts/flow/run_provenance_stack.sh.

For pinned environment baselines, profile definitions, and live environment validation, see docs/reproducible-environments.md, environments/README.md, and scripts/flow/run_reproducibility_stack.sh.

For reference Verilog-A sources plus regression-backed ngspice behavioral fallbacks, see docs/behavioral-models.md, models/behavioral/README.md, and scripts/flow/run_behavioral_model_stack.sh.

For the current RF and high-frequency passive flow, touchstone artifacts, and open-tool gaps, see docs/rf-flow.md, examples/rf/topmetal_passives/README.md, and scripts/flow/run_rf_flow.sh.

For the replayable SAR8 mixed-signal harness and its bug/trim scenarios, see docs/mixed-signal-cosim.md, scripts/mixed_signal/run_sar8_cosim.py, and scripts/flow/run_mixed_signal_cosim.sh.

For the local-first regression gate, see regression/README.md, regression/local_gates.json, and scripts/regress/run_local_regression.sh.

First real artifacts included here

• executable ngspice-friendly surrogate process and passive models
• starter SPICE wrappers for n2n_* and n2p_* devices
• starter core-cell SPICE, Verilog, Liberty, and LEF collateral
• resettable and scan-capable sequential cells plus a starter integrated clock-gate
• tie, filler, decap, antenna, tap, and endcap support-cell abstracts
• example inverter-chain and OTA smoke benches
• abstract KLayout DRC and Netgen LVS smoke harnesses
• broader positive/negative PV suites for KLayout DRC, abstract Netgen LVS, and Magic trust-boundary probing
• synthesis, OpenROAD smoke, and multi-design implementation parity scripts wired to the chosen naming scheme
• RC-aware digital and analog comparison benches plus a validated RC-stack summary tying LEF RC, OpenROAD parasitic estimates, and SPICE impact together
• metadata-driven SRAM macro views plus a placed-and-timed sram_wrap32 integration example
• a canonical interoperability snapshot plus runtime invariants for counter, gated_accum8, and sram_wrap32
• a provenance and licensing stack with deterministic source-manifest export, SHA-256 sidecars, and optional GPG signing helpers
• a reproducibility stack with a pinned validated-host tool and image baseline plus live environment validation
• a behavioral-model layer with reference Verilog-A sources plus regression-backed ngspice fallback models
• an RF passive flow that generates S1P/S2P artifacts and validates passive quality trends against the behavioral VCO baseline
• a replayable SAR8 mixed-signal cosim harness that reproduces a settling bug and a trim-improvement scenario through real RTL execution

Naming conventions

• core cells: n2_core__*
• IO cells: n2_io__*
• SRAM macros: n2_sram__*
• NMOS devices: n2n_*
• PMOS devices: n2p_*

Release caveat

This state is releaseable as an exploratory virtual PDK baseline. It is not a tapeout kit.